Dynamic fault-tolerant VLIW processor with heterogeneous Function Units

Instruction Level Parallelism (ILP) of applications is typically limited and variant in time, thus during application execution some processor Function Units (FUs) may not be used all the time. Therefore, these idle FUs can to execute replicated instructions, improving reliability. However, existing approaches either schedule instructions based on compiler or consider processors with identical FUs, able any instruction type. The former approach has a negative impact performance, whereas later applicable heterogeneous FUs. This work presents hardware mechanism for that dynamically replicates schedules both original considering space time scheduling. proposed uses small scheduling window two cycles, leading area. In order perform such flexible dynamic scheduling, switches are required, which, however, increase To reduce area overhead, cluster-based proposed, enabling scalability larger designs. implemented VEX VLIW processor. obtained results show an average speed-up 24.99% performance almost 10% power when also considered top Compared unprotected version, reliability increased by 2.2×.